Local interconnect structures are used to electrically connect different transistors fabricated on a common substrate. First and second metal layers are typically used to make these electrical contacts between certain regions of the wafer. In circuits requiring densely connected small devices, however, wiring, not active device footprint, is often the space-limiting factor.
Specifically, the first and second metallization layers seriously limit the density of many frequently used integrated circuits. For example, in conventional techniques metal layers are used to connect gates in a cross couple configuration which significantly limits density scaling due to constraints on first metal layer patterning.
Thus, a need exists to solve the local interconnect density problem to ensure continuous scaling.